1. Technical Field
The present invention generally relates to highly integrated semiconductor devices such as semiconductor memory devices and, more particularly, to an isolation structure for such devices and the methods for forming the isolation structure.
2. Description of the Related Art
An integrated circuit may be formed by connecting together various elements such as transistors which are formed on a semiconductor substrate. To ensure proper functioning of the integrated circuit, these elements must be electrically isolated from each other. Such isolation can be achieved using local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Shallow trench isolation is particularly advantageous for circuits having a high integration density since shallow trench isolation can provide for a relatively planar surface on which subsequent insulating and/or conducting layers may be formed.
A conventional process for forming a shallow trench isolation (STI) structure is shown in FIGS. 1(a)-1(f). A silicon dioxide (SiO.sub.2) layer 102 and a silicon nitride (Si.sub.3 N.sub.4) layer 104 are successively formed on the surface of a silicon substrate 100 as shown in FIG. 1(a). A patterned resist (not shown) is formed on the upper surface of silicon nitride layer 104 and an etching process such as reactive ion etching (RIE) is used to form trenches 106 in silicon substrate 100 as shown in FIG. 1(b). A thermal oxidation process is then performed to form a thermal silicon dioxide (SiO.sub.2) layer 108 on the exposed surfaces of the silicon substrate 100 as shown in FIG. 1(c). A silicon dioxide (SiO.sub.2) layer 110 is then deposited by the decomposition of TEOS, for example, to fill in trenches 106 as shown in FIG. 1(d). The silicon dioxide layer 110 is then planarized by chemical mechanical polishing (CMP), for example, as shown in FIG. 1(e). Silicon nitride layer 104 serves as a stopper layer for the planarization process. Silicon nitride layer 104 is then removed. Various wet etching processes are used in subsequent manufacturing steps to remove the silicon dioxide layer 102, as well as to remove any sacrificial or dummy silicon dioxide layers which may be formed after removal of the silicon nitride layer. Such sacrificial silicon dioxide layers may be formed to clean the substrate surface prior to growing a gate oxide layer or to repair substrate damage due, for example, to implantation processes (e.g., channel implantation processes for controlling a threshold voltage of a transistor). However, these wet etching processes cause an etching away of the silicon dioxide at the corner 112 of the shallow trench isolation structure as shown in FIG. 1(f). This etching away of the silicon dioxide at the corner of the shallow trench isolation structure is shown in more detail in FIG. 2 and can result in a lowering of the threshold voltage of a transistor formed in the active area defined by the shallow trench isolation structure.
One technique of protecting the corner of a shallow trench isolation structure is described in U.S. Pat. No. 5,521,422 to Mandelman et al. In one embodiment of the Mandelman et al. process shown in FIGS. 3(a)-3(f), a pad oxide 10 and a nitride surface coating 12 are successively formed on the surface of a silicon substrate 5. The nitride surface coating 12 is then etched to form an opening 14 as shown in FIG. 3(a). Next, an insulator 16 such as a CVD oxide is deposited as shown in FIG. 3(b) and layer 16 and layer 10 are then etched as shown in FIG. 3(c) to leave spacers 16a and 16b on the sidewalls of the nitride surface coating. A trench 18, defined by the spacers 16a and 16b, is then formed in the silicon substrate 5 as shown in FIG. 3(d). An insulator 20 is deposited to fill trench 18 and opening 14. Insulator 20 is then planarized, stopping on nitride surface coating 12. Nitride surface coating 12 is then removed, leaving insulator 20 with spacers 16a and 16b extending above the surface of silicon substrate 5 as shown in FIG. 3(e). Subsequently, pad oxide 10 is etched and a gate dielectric 22 is formed. A gate conductor 24 is then deposited and photolithographically defined as shown in FIG. 3(f).
While the Mandelman et al. process protects the corner of the shallow trench isolation structure from attack during subsequent etching processes, several problems can arise. In particular, the protection of the corner of the shallow trench isolation structure depends on the length "L" shown in FIG. 4. The length "L" refers to the distance that the sidewalls 16a and 16b extend from the corners of the shallow trench isolation structure. Variations in this length "L" can lead to variations in the shape of the shallow trench isolation structures, particularly if the length "L" is varied to be too small such that subsequent etching processes result in the removal of the sidewalls and the attack of the corner of the shallow trench isolation structure. This can result in fluctuations in the device characteristics. Accordingly, the length "L" must be accurately controlled to ensure protection of the corners of the shallow trench isolation structure. In the Mandelman et al. process, the length "L" is determined by the thickness of the insulator 16 deposited during the deposition step shown in FIG. 3(b) and the amount of the insulator 16 which is etched during the reactive ion etching step of FIG. 3(c). Since the length "L" depends on the uniformity of both of these processes and since the uniformity of both of these processes can be affected by, inter alia, wafer position (e.g., center of wafer versus peripheral portion of wafer), the length "L" can be difficult to control in the Mandelman et al. process, leading to possible fluctuations in device characteristics.
In addition, as can be seen in FIG. 3(f), insulator 20 and sidewall spacers 16a and 16b extend above the surface of silicon substrate 5. A step is formed inevitably on the gate electrode 24 since there is a difference in level created between the surface of silicon substrate 5 and the insulator 20. This can lead to difficulties in the patterning of the gate conductor 24, particularly in highly integrated devices such as 64 Mbit and 256 Mbit dynamic random access memories (DRAMs).
Further, the process of Mandelman et al. requires a number of additional steps as compared to the conventional process of FIGS. 1(a)-1(f), e.g., the deposition of insulator 16 and the etching of insulator 16.
Accordingly, it would be desirable to provide a shallow trench isolation structure and methods for forming the shallow trench isolation structure which avoid these and other problems.